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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. !!" # !" # $% & !& #'( ) *+& #, $$& - "'. "$%& '! /" 01 !$" ! *+ &! 2 & & 3 4 & ! " # *+ ( " & ! , *+ ( !,!!5 " ! ! 4 &, , " *+' " " & ! , & &! , 5 " " !$" !*+ 1 !$" !*+& (" "$ ? 6!!# #"# *+'5 " !!4 !, & !34 ? ! ! 3 !! #7 3 ! + ? 8 $" ! !! #$" ! ! + ? 9 4 !! # 4 ! + ? 7# !8 #.9 :9 ? ; &<( ! ? 7 !4 "= ? * ! # ? , "* ! #=>68= 4 ? = 0='&, " & ? + &" 4 5 " &" 4 ? + ," !,," ? 8='80'84 ? ? 4!@ @ @ &5&&!# ? ( , >. //. ? *,"#!>= %#!a= " )"!*!+', '! b4 ? $!3 * , " $" ! 3 4 58 8 3 ,<# ! # * -? +c . # ( , = 0=d1+1e 6 8=8 @@ ? ' " " ! =1&! = 00d1+1e 6 0808 = / b(( = 0d1+1e 6 =88 = . //. = ' " 68= 4 ? '&, " & " - ,." pd4 5 v 128 8 2 1 g5 - a75 [ x4, x8 ] interface 1 : lvttl number of banks and channel 1 : 2 banks and 8 channels 2 : 2 banks and 16 channels 3 : 2 banks and 32 channels 4 : 4 banks and 8 channels 5 : 4 banks and 16 channels 6 : 4 banks and 32 channels organization 4 : x4 8 : x8 dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v minimum cycle time 75 : rl=2 : 7.5 ns (133 mhz) 10 : rl=2 : 10 ns (100 mhz) v : virtualchannel memory memory density 64m bits 128m bits : : 64 128 note note note note note no letter : single data rate sdram category " pd4 5 v 128 16 1 g5 - a75 [ x16 ] number of banks and interface 1 : 2 banks and lvttl word and number of channel memory density dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v category 64m bits 128m bits : : 64 128 note note 15 : x16 bits and 8 channels 16 : x16 bits and 16 channels 17 : x16 bits and 32 channels no letter : single data rate sdram minimum cycle time 75 : rl=2 : 7.5 ns (133 mhz) 10 : rl=2 : 10 ns (100 mhz) v : virtualchannel memory " ! '!+* '!$ a888 !54 ! / 0 &! $ %12134,,13322 5')$6. $6. !7$ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss nc v ss q nc dq3 v cc q nc nc v ss q nc dq2 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a7, a10 dq0 - dq3 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs / outputs chip select row address strobe column address strobe write enable dqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input / output pin function for bank address, channel address and segment address. " / 0 &! $ %12134,,13322 5')$6. $6. !7$ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a7 dq0 - dq7 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs / outputs chip select row address strobe column address strobe write enable dqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input / output pin function for bank address, channel address and segment address. " 8 / 0 &! $ %12134,,13322 5')$6. $6. !7$ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc ldqm /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a6 dq0 - dq15 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs / outputs chip select row address strobe column address strobe write enable udqm ldqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : : upper dq mask enable lower dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input / output pin function for bank address, channel address and segment address. " !!" % "% " /" !$" ! *+ # "!4# 4 & # "4"& ,,# ! ! # , ( , 8 4 # # ' " !$" ! *+ "!4# !#, 5 4, &&! " ! $'d "'( f /" !5 & # " *+' 6! " # 3 *b 4 # 4, &, & 5 " !$" !*+ "!4# / #g # # # ! &! 3a # ' 534 ! 34 " # # 5 " ! ! # 5 " ! ! #' !3 ? , 4 !$" ! *+ " 4 , " ! 34' ! &! ' ! 4 /" !$" !*+&# 5 " !$" ! " " ! , " , & " , " # " # /" !$" ! 5!! ? " " ! 4 , " # g ' " ! # , ! " 4 " " ! <&& 5 " 5 ,, 5 & & 4 / " # ' "!3!3 5#, # /"# # !! "" ! " # , " /"' "" ! 3 " , "# /"# # !!" &! ! "& , "" ! ( "! " 4 ,#5 ! "" !, , "" ! 5 3 "#5 +#" ! " , #5' 5 #5 " ,!!# /" "* ; & 5!! 4 " & !5 " " "4"&" !'?4 !!" 5 " "*+ 3& /"* a; & , "" !,4& & & !#5 " "*+ 3 & 34 & , + ' " 4' , " . 4 5 " ! * ; 4 " ! 5 /" !$" ! *+ ! , " " &, # !!54 " # # !! "! ",4 34& & !# !!" % "% "'++"$ "+' '5!*+" "$ !)."!"+ $9 ! &! ",, "4"& &, , !*+ +"4! ,!! 5 "5 "!5! #' ! 5' !* a; "4" "" ! @ / & *+ 3& "4" " ,4 7 34b& = #5 # 5 ! , 5$" ! # < ! , , ! &! # 3 # 4 !# , , " ,<# , *5 + " 4, !*+ " : '%7 * , channel bank b sense amp. memory cell array row decoder segment decoder dqm control logic command decoder clock generator cke clk bank a column decoder latch circuit data control circuit input and output buffer dq dq address buffer and refresh counter address address channel control channel selector /we /cas /ras /cs " 3 '!%"& % ", % foreground read operation write operation row decoder bank b row decoder bank a one segment : 1/4 row one segment means one data transfer size at the background operations. background prefetch operation restore operation prefetch operation (from segment of memory core to channel) restore operation (from channel to segment of memory core) write operation ( to channel ) read operation ( from channel ) 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment " '!%"& % ", % prefetch operation the data is fetched from a segment to any channel buffer. segment segment segment segment segment segment segment segment 16 channels row decoder bank b row decoder bank a restore operation the data is transferred from a channel buffer to any segment. 16 channels row decoder bank b row decoder bank a segment segment segment segment segment segment segment segment must select one channel must select one segment " $;"'+$"*,"! !)% !!" memory cell 8 k (8192) bits 1 row 2 k (2048) bits 4 segments 16 channels 2 k (2048) bits 2 1 3 45 16 input and output buffer 0 1 2 3 x 4 bits organization 512 bits 2048 (2k) bits / 4 column selector one channel density 2048 (2k) bits input and output buffer 0 1 2 3 4 5 7 6 x 8 bits organization column selector 256 bits 2048 (2k) bits / 8 one channel density 2048 (2k) bits input and output buffer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x 16 bits organization column selector 128 bits 2048 (2k) bits / 16 one channel density 2048 (2k) bits one segment means one data transfer size at the prefetch and restore operation. " - 4!& < & !( !% '! a@ (& ab & 6 $.% (& $.% " !3& b "& 4 !, !! , "$.%44 $% (& $% ! #, "8 $.%!3 (,$% "4"' "8 $.%4 4 !h "5 ! (, "$.%44 !' " ! !3 " !$" !*+&& ;" " !$" !*+ $% 4 ' " &55 4&55'$% !5 a$ (& $"&! a$ !5 " & #!'5""44,$.% 4a$ "4"' 4 & a*+ 'a$+ 'a; (& $ (& /" , "4 !, " 4 6 !', "$ / !$ 6 /"# ! a*+ 'a$+ 'a; , ", ! 4, !*+ 9 680'8= :9.9 68 (& 68='80 9 !(ab ,, 68 :9 .9 !&& # !5 # (ab ,,'& !# !" ),')" 9 ! " & ,,!3 !ab & 9"4" 9!5 " & ,,,, '& !# /"9! #, " 5!3 !5 ",')" 9 ! "5 3 (& 5 "#!!,9 !5 ,9"4" /"9! #, "5 ? 9 19@ 9 19 9 19 (& a b & 9&" " , (ab& #"*+ 9 19@,8= 9 19,80 9 190,8 $ ? . "& $$ 5&&!# $$ &5&&!#&, ! $$ 9 9 5&&!# $$ 9 9 &5&&!#&, " & ,, " a@ (& a b & 6 + 1+@ (& +&, /"&&# 4 3'5'!' ' " ! '5 ))"$$ *5+ #+ 1+ "$.%!344 " #! ( & " 4 ? ' ,! ))"$$ $!+ #+ 1+ + "$.%44 " 5 #! ( & " 4 ? >+ 1+'+ ,8= >+ 1+,80 >+ 1+,8 !7 ))"$$1 -2 +@ " 3! 4 ! ( #!'+@!5! 3+' +@"4"! 37 !!" ))"$$1 : 2 +0'+e'+'+ "" !! 4 ! channel number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 "*,"! ))"$$1 3 3 -2 + '+'+ '+@ "4 ! 4 ! in prefetch and restore operations, column address in channel is determined by a0, a1. in prefetch read operation, segment is determined by a10, a13. " @a@ (& a b & 6 + 1+@ (& '&"% *" ))"$$1 32 + , "&" 4 ( "&" 4 #! -4"!!>+!! 3 &" 4 .5!!>b!# " 3! #+@&" 4 ( "&, " #! -4"!!>+ &" 4 .5!!>; " &" 4 " 4 . " 4 ',, !)6"% '! +!! 8 5 " "4 ! "44, "!3$.%'a$ $"& ! !5 " & #! $% $!3 ! "4" !3 , " & #! "5 !5 /" , "a*+ 'a$+ ' a; 4 !&, " , 8 " " 4 ! ,a*+ 'a$+ ' a; 4" # , & 4 ! ;"a$ "4"'& &, " ' , " 4 ! " 5!&,# 4 !a$ !5 /" ! /ras /cas /we address cke clk h n - 1 n n + 1 command l /cs " 8 4 ',, !) . " ! . -8 8888888888888888 & b . - - - 8 8 8 8 8 8 8 8 8 8 8 8 8 8 , "5 " &" 4 6$ . - - . 7+ $" $" . $" $" . . . 8 8 8 4 4 , "5 " &" 4 6$+ . - - . 7+ $" $" - $" $" . . . 8 8 8 4 4 * 5 " &" 4 * / . - - . 7+ $" $" . $" $" - 8 8 8 8 8 4 4 * 5 " &" 4 * /+ . - - . 7+ $" $" - $" $" - 8 8 8 8 8 4 4 $" ! * + . - . - 8 $" $" $! $" $" $! $! $! $! $! $! $! $! $" !5 ;*(/ . - . . . $" $" $! $" $" $! $! $! $! $! $! $! $! 7 3 +$/ . . - - 7+ *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 , " 5 " &" 4 6* ' " . . - . 4 $" $" 4 $" $" $! $! $! $! $! $! $! $! " 4! 3 * . . . . 7+ 8 8 . 8 8 8 8 . 8 8 8 8 8 " 4 !! 3 +.. . . . . 8 8 8 - 8 8 8 8 . 8 8 8 8 8 * * / . . . . . . . . . . . . - 8 8 8 8 8 ' " 68= 4 ? ' " !!4 ! ", 7 + " ! ,!!5 - >-4"!! . >.5!! c >-4".5!!g *5 >*5 $! >$! 7+ >7 3+ $" >$" ! 4 > 4 " 4- = . " $ 6 # ! $% a$ a*+ a$+ a; + i + 4 $!3& # i - . 8 8 8 8 8 +# $!3& i . . 8 8 8 8 8 $!3& $!3&8 i . - 8 8 8 8 8 (! + ," * 6 - - . . . - 8 (! !,," # .6 - . . . . - 8 !,," !,,"8 i . - . - - - 8 .- -8888 (! 55 # i - . 8 8 8 8 8 55 558 i . - - 8 8 8 8 .---8 ", 7 ->-4"!!'.>.5!!'8>-4".5!!g " : -4 ',, !)$ ">%")"$" "% 1 ?2 -4" 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ", 7 8>-4".5!!g /"! # " clk cke h /ras /we /cas a0 to a13 /cs " 3 ''&" '!12 .5 -4" -4" -4" 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ", 7 8>-4".5!!g /" 8 & 4 # " /cs clk cke h /ras /we /cas a0 to a13 " "+" % 5 ' '&"% *"1( 2 .5 -4" -4" .5 7+ $" $" .5 $" $" .5 .5 .5 8 8 8 4 4 ", 7 7+>7 3 '$" >$" ! '8>-4".5!!g ' 4 > 4 /" ,!!57 3 +$/ /" , " , 4 , " 5 3 " ! ,,5""" #" ! /" 4 7 3,! &,# "4 3 ( ' "$" !+,!&, " " ! + &,# "& !&" 4& ( ,+ >!5'5 " &" 4& ( ,+ >"4"'5 " &" 4& , , "& ! , ( 7 3&" 4 # , , " /", " !#5 " #&" 4& 6 '5" ", & " ,,4 5 ," !', "&, " & <, 5' ,, " !' "&, " 5 " #&" 4& 6$ 6$a6$+ &< 5, &, " ;" "55 3' 3&" 4 # , "6$ . 6$ * &< 56$ * 6 " "" ! ,, ! !,$" !* $" !; & /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a4 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid a6 a5 " "+" % 5 '&"% *"1( 2 .5 -4" -4" .5 7+ $" $" -4" $" $" .5 .5 .5 8 8 8 4 4 ", 7 7+>7 3 '$" >$" ! '8>-4".5!!g ' 4 > 4 /" ,!!57 3 +$/ /" , " , 4 , " 5 3 " ! ,,' &" 4 & &, !!#' 5"" ! " 5 , , "& /" 4 7 3,!&,# "4 3 ( ' "$" !+,!&, " " ! + &,# "& !&" 4& ( ,+ >!5'5 " &" 4& ! , ( ( ,+ >"4"'5 " &" 4& , , "& 6 " "" ! ,, ! !,$" !* $" !; & /cs clk cke h /we /cas a13 valid a12 valid a1 valid /ras a2 to a4 bank select channel address a11 valid a9 valid channel address a8 valid a7 segment address a0 valid a6 a5 a10 " - "$ '"5 ' '&"% *"1 2 .5 -4" -4" .5 7+ $" $" .5 $" $" -4" 8 8 8 8 8 4 4 ", 7 7+>7 3 '$" >$" ! '8>-4".5!!g ' 4 > 4 /" , , " ! ,, 4 , 55""44 # ,!!54+$/ /" 7 3+,!&, " 3 /"$" !+,!&,# "" ! /" 4 ,!&, " 4 + &,# "& !&" 4& ( ,+ >!5'5 " &" 4& ( ,+ >"4"'5 " &" 4& , , "& ! , /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a6 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid " "$ '"5 '&"% *"1 2 .5 -4" -4" .5 7+ $" $" -4" $" $" -4" 8 8 8 8 8 4 4 ", 7 7+>7 3 '$" >$" ! '8>-4".5!!g ' 4 > 4 /" , , " ! ,, 4 , 55""44 # ,!!54+$/ ( '&" 4& &, !!#5""! " 5 , & /" 7 3+,!&, " 3 /"$" !+,!&,# "" ! /" 4 ,!&, " 4 + &,# "& !&" 4& ( ,+ >!5'5 " &" 4& ! , ( ,+ >"4"'5 " &" 4& , , "& /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a6 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid " !!" " )1 2 .5 -4" .5 -4" 8 $" $" $! $" $" $! $! $! $! $! $! $! $! ", 7 8>-4".5!!g '$" >$ " ! '$! >$! $" !* * + 5, " ! ,, " 9 /"$" !+,! &, "" ! /"$!+,!&, " 4! , " 5 " ,, 5 # ='0' /cs clk cke h /ras /we /cas a13 a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address a10 valid column address " !!" 5 "1@ 2 .5 -4" .5 .5 .5 $" $" $! $" $" $! $! $! $! $! $! $! $! ", 7 8>-4".5!!g '$" >$ " ! '$! >$! $" !; ;*(/5 , " 9 " ! ,, /"$" !+,!&, " " ! /"$!+,!&, " 4! , " 5 " ,, 5 # ='0 /cs clk cke h /ras /we /cas a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address a10 valid column address a13 " 8 !7 % > "1 2 .5 .5 -4" -4" 7+ *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 *5 ", 7 7+>7 3 '*5>*5 + 5 &! " 3g &!, /" 7 3+ *5+,!&,# 3 5 /"" 5 3' "5 "0'e5 /" " 3! # 3 +@ 5 ! #+ "4"+ /"5 , ! " 4 " 3 +" 4 , "5 " 3 " 3 " 5 /" & !*+ja*+ , !!4 /cs clk cke h /ras /we /cas a13 a0 to a12 valid valid bank select row address " "+" % " )5 '&"% *"1( 2 .5 .5 -4" .5 4 $" $" 4 $" $" $! $! $! $! $! $! $! $! ", 7 4 > 4 '$" >$" ! '$! >$! /" ,!!57 3 +$/ /" , " , 4 , " 5 3 " ! ,,' 5, " ! ,, " 9 ( ' &" 4 & &, !!#' 5"" ! " 5 , , " & /" 4 ,! &,# " 4 ( ' " $" ! + ,! &, " " ! /"$!+,!&, " 4! , " 5 " ,, 5 # ='0' 68= 4 ? ' " !!4 ! /cs clk cke h /we a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address /ras /cas segment address a13 valid segment address a10 valid " : "% *"$" "% "). !71 2 .5 .5 .5 .5 7+ 8 8 .5 8 8 8 8 .5 8 8 8 8 8 ", 7 7+>7 3 '8>-4".5!!g /" ! 5 3' && " 3 , + * 55 +, &" 44' 3 "(! /"7 3,!&, " 3 &" 4 + .5&, " +, " ' * &" 4 & , , 8 &" 44 3 /" & !*+ja*+ 4 /cs clk cke h /we /ras a6 to a9 a11,a12 a10 a13 valid bank select /cas a0 to a4 a5 " -3 "% *" . !7$1 ??2 .5 .5 .5 .5 8 8 8 -4" 8 8 8 8 .5 8 8 8 8 8 ", 7 8>-4".5!!g /"4 ! *5 " ,+ -4" /"+.. #& !!# 4 ,"& !? *&! 5 "" 4 , " 3 /cs clk cke h /we /ras a6 to a9 a11 to a13 /cas a0 to a4 a5 a10 " - "$" 1 2 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 -4" 8 8 8 8 8 ", 7 8>-4".5!!j /" !? !$" !*+ /cs clk cke h /ras /we /cas a6 to a13 a5 a0 to a4 " - ' "+"$ 1 (2 -4"-4" .5 .5 .5 -4" 8 ", 7 8>-4".5!!j /" < 4 " ,"& /"," 4 !!# 7,8 4 ,"' !! 3 "! +, "#!' !! 35!! "! &" 4 #, 5 4 *$ &,," ," ' " !$" !*+ & # " clk cke h n ? 1n /ras /cas a0 to a13 h /we /cs " -- " + "+"$ 1?(2 -4".5 .5 .5 .5 -4" 8 ", 7 8>-4".5!!j +, " 8 '!,,"& 5"!$% !5 4!,,"' " !," !! 3 ,," ! ,"& /",8 ! ! 7,8 4!,,"' " 3 "! 4!,,"' " 34 ,4& 8 /cs clk cke /ras n ? 1n /cas a0 to a13 hl /we " - 4,& +") " * , active stand by active power down prefetch with auto precharge auto refresh precharge restore with auto precharge self refresh power down reset channel read channel write automatic sequence manual input background operation foreground operation restore without auto precharge prefetch without auto precharge prefetch read write suspend read suspend idle stand by power on cke:low cke:high cke:low cke:high writ read cke:low cke:high self self exit pre rest ref pfc row active cke:high cke:low read read act read r ead read read read read pfr pre pre pre pre rst rst rst rsta rsta rsta act act act writ writ writ writ writ writ writ pfc pfca pfca pfca pfca pfc pfc act read w r it " - 4"+" % " )&" '! ( ( ( ( & '! ) ) ) ) /"& , " , 4 , " 5 3 " ! ,,' 5 , " ! ,, " 9 ( '&" 4& &, !!#'5"" ! " 5 , , "& 68= 4 ? '&, " & 6* !!4 ! row decoder bank b row decoder bank a read operation 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment prefetch read operation prefetch operation clk command dq act pfc read q2 q1 q0 0 2345678 1 hi-z ( burst length = 4 ) q3 command act pfr dq q1 q0 hi-z q2 q3 read latency = 2 prefetch read latency = 4 t apd t aprd "" '!$ &." 5""!% '%7+"a "!%b !)" ) "!%b&"+" % " ) "!%b $!3,<#-?+c * ! # , " ! # @@ = " - 4@ "&" '! !) "$ '"&" '! ; &5 & "" ! ;" "# ,!! "" !5 "5 ' & # # /" & " * , * & !,!!# & /" "" ! , #5"# # + "5 & "" ! &4 " & /" " 34& !!4 !5"! *+ * /a* /+ +$/* ! # ( ' ",4& " " ! #* / !!4 ! row decoder bank b row decoder bank a restore operation (from channel to segment) write operation ( to channel ) 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d1-1 d1-0 0 2345678 1 t ras t rcd hi-z ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 remark act(r) command is act command after rst command. without auto precharge col. 1 banka channel 1 with auto precharge q1-1 d1-2 d1-3 9 10 read " -8 84 $%" !*$ +, !? ' !!# ! #' !4 " 5 &< ,!!5 ( ! * ! # , " . # = 7 !4 " = ; &< ( ! ( " ! 84 $ ?"!* !)"a "!%" / $ '+(' 0 4+ +4 < ! +'+ ( ! # ! '''@ ' '@' '@' ' @''' " - 4! ; '! /" !$" !*+ !? "&51< 4 ",!!54 / !? ! '5"&5 &&!' !4& & #4 ! 44!4 +, "& ' " 3 &" 44 "" 4 /"" 4 !! 3 @ b "&" 4&! " * ,' " 8 8 !& ! = +, " #!' * $ $.%& , 5!! /5 ," &, ", 7$4 /" *," # & 4 $% 9 "!"4" ! "" 4 1 -1k " -: :4 "% % &"%+% '!$ ? +!!! 4 , d ? +, &5 &' 5 " "' 8 '5"'!$"a "!%" !) ' "+"$ , && & " .$' " 6, , !*$ # ! $ * 4 : ! 4&5&&!#&! d $$ ' $$ 9 i l= ! 4& &! d / i l= " & ( b + 5& ; b& 4 & / + $ 4 & / 4 i l $ '! 6&'$!* " )">%" ' $ "$$ .'>" '$" $ ") ! .$' " 6, , !*$ %' ) % $" &", !"! ) , *"4 ")">%"$!' ," ! '."'&" ") !)"%'!) '!$' $)" " , $ )"$%.")! "'&" '! $"% '!'+ $$&"%+% '!46&'$ " ' .$' " 6, , !* %'!) '!$+'"6 "!)")&"')$, b ++"% )">%"" . b4 "%',,"!)")&" !* '!) '!$ # ! $ ( /m +c : &&!#! 4 $$ ' $$ 9 @ @ @ @ -4"!!& ! 4 (- $$ l @ ' " .5!!& ! 4 (. i @ ' " l 0 b& 4 & / + $ ' "$4 (-+c n $$ l !5 " 4 (.( ni !5 " & % !%"1 c +c#;2 # ! / ( /m +c : (& & $ ( $.% @ &6 $ ( + 1+@'$% 'a$ 'a*+ 'a$+ 'a; ' @ 0 9':9'.9 & a & & $ (ab 9 = &6 " 3 % "$ %$1 "%',,"!)")&" !* '!) '!$ ! "$$' "5$"!' ")2 # ! / 8 : 8= 80 8 b& 4 ( $$ *$ *$( + , " , "8 4 *$ 3 b& 4 ( $$ * *$ *$( + * 3 " 4 # ( $$ $% (.+c ' $% n + &55 ( $$ $% (.+c ' $% n " 4 # ( $$ $% (-( ' $% n 'a$ (-( + &55 (& 4 ! " 4 4@ ( $$ $% (-( ' $% n '(& 4 ! ! + # ( $$@ $% (.+c ' $% n + &55 ( $$@ $% (.+c ' $% n + # ( $$@ $% (-( ' $% n 'a$ (-( @ + &55 (& 4 ! " 4 4@ ( $$@ $% (-( ' $% n '(& 4 ! ! b& 4 ( $$= $% $%( '( b n +' + 7 7 34>&" 4 # + ," ( $$ *$6 *$6( @ +@ !,," ( $$ $% + ' "$4 ( $$ &#! ( "'( $$ " " 4 !# 4 $%( ( $$= & & ! 4 #! &, ! 5 " " & & ( "'( $$= " " 4!# 4 $%( -4 ( $$ " " 4!# 4 $%( % "$ %$1 "%',,"!)")&" !* '!) '!$ ! "$$' "5$"!' ")2 # ! / ( /m +c : (& ! 3 4 ( (. ( $$ 9' $$ 9n $$ +!! "& n i i l + b & ! 3 4 ( b. b $$ 9' b:/ ! i i l + -4"!! & ! 4 b- ( b ni= + = i i .5!! & ! 4 b. ( b nl= + i i = " % "$ %$1 "%',,"!)")&" !* '!) '!$ ! "$$' "5$"!' ")2 "$ '!) '!$ ? +$ / n ? *,!!, 4 4,& 4 ! = / 5 (- (. ? (, / !4 " ',!!, 4 4,& 4 ! (-( (.+c ? + = t ck2 t s t h t ds valid valid valid valid valid t ac2 hi-z hi-z t ac2 t lz t oh2 t hz t dh t ds t dh t ch t ch t cl clk (input) command address dqm data (input) data (output) cke t cks t ckh t ck2 t cl " % % "$ %$ # ! 1+ : ( +c $!3#! $% ? + ,$.% +$ ? = $.%"4"!!5 " $- ? $.%!5!!5 " $. ? 1 "! b- ? 1 !51& .k ? 1 "4"1& -k = 1 & ? 1"! - 0 ? +'$ '9 & ? +'$ '9"! - 0 ? $% & $% ? $% "! $%- 0 ? $% & 558 $% ? / / @ *," =' e,"#! * 6 ? = * #! * $ ? $.% ' " b & ! output z = 50 ? 50 pf " - % % "$ %$1 %7*' !) ' %7*' !)'&" '!2 # ! 1+ : ( +c !"#$%" +$/ +$/a* 6$ & *$ ? * 6 * 6a+$/$ & *$6 ? +$/ * $ & *+ ' * +$/a* 6$ & * ? +$/ 6$a6$+$ ! # + ? +$/ 6*$ ! # , "* b& +* ? 6$ * $ ! # . ? 6$+a6* +$/a* 6$ ! # +. = ? * /a* /+ +$/* ' " $ ! # *+ @ @ &"$' !"#$%" +$/* ' " 6$a6$+a6* $ ! # * @ ? 6$ 6$a6$+$ ! # ? "$' !"#$%" +$/ +$/a+$/*+$/* +$/ $ ! # ** ? +$/* +$/*$ ! # *** @ ? 6$a6$+ * /a* /+$ ! # * ? ' "$4 +$/* +$/ , * / 4 68= 4 ? '&, " & -4 /" " 34& " !,4& !!4 !5"! *+ & " % % "$ %$1('"*' !) '('"*' !)'&" '!2 # ! 1+ : ( +c * +a;*(/ * +a;*(/ $ ! # $$ ? % % "$ %$1 %7*' !) '('"*' !)'&" '!2 1 + "$ ,"% !!" "+" % < "$ '"2 # ! 1+ : ( +c 6$a6$+ * +a;*(/ $ ! # $ ? +$/* * +a;*(/ $ ! # *$ @ ? ' " +$/* +$/ , * / data sheet e0025n10 45 pd45v128421, 45v128821, 45v128161 power on sequence and auto refresh clk 41213 22 21 command address a10 t rp pall h ref row 1 act banka t rsc ref a5 l t rcf t rcf dq dqm hi-z 0123 rest remark rest command can be executed one or more times. data sheet e0025n10 46 pd45v128421, 45v128821, 45v128161 /cs function (only /cs signal needs to be issued at minimum rate) clk ( read latency = 2, burst length = 4 ) 0 2345678 1 9 111213141516 10 command act pfc read writ cke /ras /cas /we /cs dq dqm l hi-z q1-0 q1-1 d1-0 d1-1 a8,a9,a11,a12 row channel channel channel a13 bank bank a10 row a5,a6,a7 row column column a2,a3,a4 row column column a0,a1 row segment column column h q1-2 q1-3 d1-2 d1-3 data sheet e0025n10 47 pd45v128421, 45v128821, 45v128161 clock suspension during burst read (using cke function) clk command channel address a13 a10 dq dqm ( read latency = 2, burst length = 4 ) 0 2345678 1 t apd l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 read channel 1 hi-z q1-3 t pcd cke q1-0 q1-1 q1-2 auto precharge without 1 clock suspend 2 clocks suspend 3 clocks suspend data sheet e0025n10 48 pd45v128421, 45v128821, 45v128161 clock suspension during burst write (using cke function) clk command channel address a13 a10 dq dqm ( burst length = 4 ) 0 2345678 1 t apd l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 writ channel 1 hi-z t pcd cke d1-0 auto precharge without 1 clock suspend 2 clocks suspend 3 clocks suspend d1-1 d1-2 d1-3 data sheet e0025n10 49 pd45v128421, 45v128821, 45v128161 power down mode clk command channel address a13 a10 dq dqm ( read latency = 2, burst length = 4 ) 0 2345678 1 l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 read channel 1 hi-z cke q1-0 q1-1 auto precharge without power down mode entry power down mode exit power down mode entry power down mode exit t cksp t cksp pre banka l active standby precharge standby q1-2 q1-3 data sheet e0025n10 50 pd45v128421, 45v128821, 45v128161 read operation read 0234 1 clk command dq dqm q0 q1 q2 hi-z l q3 ( burst length = 4 ) read latency = 2 write operation writ 023 1 clk command dq dqm d1 d2 d3 l ( burst length = 4 ) write latency = 0 d0 data sheet e0025n10 51 pd45v128421, 45v128821, 45v128161 dqm operation in read clk dq dqm q0 q1 q3 hi-z hi-z read mask latency = 2 mask ( burst length = 4 ) dqm operation in write clk dq dqm mask mask ( burst length = 4 ) d1 d3 write mask latency = 0 data sheet e0025n10 52 pd45v128421, 45v128821, 45v128161 read to read operation clk command channel address dq dqm read col. 0 col. 0 read 0 2345678 1 t ccd hi-z l q1-0 q1-1 q1-2 q1-3 q3-0 q3-1 q3-2 channel 1 channel 3 ( read latency = 2, burst length = 4 ) q3-3 write to write operation clk command channel address dq dqm writ col. 0 col. 0 writ 0 2345678 1 t ccd hi-z l d1-0 d1-1 d1-2 d1-3 d3-0 d3-1 d3-2 d3-3 ( burst length = 4 ) channel 1 channel 3 data sheet e0025n10 53 pd45v128421, 45v128821, 45v128161 read to write operation clk command channel address dq dqm read col. 0 col. 0 writ 0 2345678 1 t ccd hi-z l q1-0 q1-1 q1-2 d3-0 d3-1 d3-2 ( burst length = 4 ) channel 1 channel 3 d3-3 write to read operation clk command channel address dq dqm writ col. 0 col. 0 read 0 2345678 1 t ccd hi-z hi-z l d1-0 d1-1 d1-2 q3-0 q3-1 q3-2 ( burst length = 4 ) channel 1 channel 3 q3-3 data sheet e0025n10 54 pd45v128421, 45v128821, 45v128161 prefetch to read operation without auto precharge (same channel read) clk command channel address a13 a10 dq dqm act pfc read pre act row 0 banka row 1 banka col. 0 banka banka l q1-2 q1-1 q1-0 0 2345678 1 t apd t ras t rc t rp t pcd hi-z l ( read latency = 2, burst length = 4 ) channel 1 channel 1 segment without auto precharge q1-3 prefetch to read operation without auto precharge (other channel read) clk command channel address a13 a10 dq dqm act pfc read read pre row 0 banka col. 7 col. 0 banka banka l q4-2 q5-7 q4-1 q4-0 0 2345678 1 t ppl hi-z l ( read latency = 2, burst length = 4 ) channel 1 segment channel 4 channel 5 without auto precharge data sheet e0025n10 55 pd45v128421, 45v128821, 45v128161 prefetch to write operation without auto precharge (same channel write) clk command channel address a13 a10 dq dqm act act pfc writ pre row 0 banka row 1 col. 0 banka banka banka l d1-2 d1-3 d1-1 d1-0 0 2345678 1 t apd t ras t rc t pcd t rp hi-z l ( burst length = 4 ) channel 1 segment channel 1 without auto precharge prefetch to write operation without auto precharge (other channel write) clk command channel address a13 a10 dq dqm pfc act writ pre writ row 0 banka col. 7 col. 0 banka banka l d4-2 d3-7 d3-8 d4-1 d4-0 0 2345678 1 t ppl hi-z l ( burst length = 4 ) channel 1 segment channel 4 channel 3 d3-9 without auto precharge data sheet e0025n10 56 pd45v128421, 45v128821, 45v128161 read to prefetch to read operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm pfc read act read pre row 0 banka col. 7 col. 0 banka banka l q1-2 q1-1 q1-0 q1-7 0 2345678 1 t apd t pcd t ppl hi-z prefetch termination ( read latency = 2, burst length = 4 ) channel 1 segment channel 1 channel 1 without auto precharge q1-9 q1-8 read to prefetch to write operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm pfc read act writ pre row 0 banka col. 3 col. 0 banka banka l d1-3 q1-1 q1-0 d1-5 d1-4 0 2345678 1 t apd t pcd t ppl hi-z prefetch termination channel 1 segment channel 1 channel 1 ( read latency = 2, burst length = 4 ) without auto precharge d1-6 data sheet e0025n10 57 pd45v128421, 45v128821, 45v128161 write to prefetch to write operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm act writ writ pre row 0 banka col. 1 col. 0 banka banka l d1-2 d1-1 d1-1 d1-0 d1-2 d1-3 0 2345678 1 t apd t ppl t pcd hi-z mask pfc ( burst length = 4 ) segment channel 1 channel 1 channel 1 d1-4 without auto precharge d1-3 write to prefetch to read operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm act writ read pre row 0 banka col. 1 col. 0 banka banka l d1-2 d1-1 d1-0 q1-2 d1-3 q1-1 0 2345678 1 t apd t ppl t pcd hi-z mask pfc ( read latency = 2, burst length = 4 ) segment channel 1 channel 1 channel 1 without auto precharge data sheet e0025n10 58 pd45v128421, 45v128821, 45v128161 restore to read operation without auto precharge (same channel read) clk command channel address a13 a10 dq dqm read pre row 0 col. 0 banka l q1-1 q1-0 0 2345678 1 t rcd t ras hi-z l ( read latency = 2, burst length = 4 ) segment channel 1 channel 1 t rad rst act (r) banka banka remark act(r) command is act command after rst command. without auto precharge q1-2 restore to read operation without auto precharge (other channel read) clk command channel address a13 a10 dq dqm read pre row 0 col. 0 banka l q7-3 q7-2 q7-1 q7-0 0 2345678 1 t ras hi-z l ( read latency = 2, burst length = 4 ) segment channel 7 channel 1 t rad rst act (r) banka banka remark act(r) command is act command after rst command. without auto precharge data sheet e0025n10 59 pd45v128421, 45v128821, 45v128161 restore to write operation without auto precharge (same channel write) clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d1-3 d1-2 d1-1 d1-0 0 2345678 1 t ras t rcd hi-z l ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 remark act(r) command is act command after rst command. without auto precharge restore to write operation without auto precharge (other channel write) clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d3-3 d3-2 d3-1 d3-0 0 2345678 1 t ras hi-z l ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 3 remark act(r) command is act command after rst command. without auto precharge data sheet e0025n10 60 pd45v128421, 45v128821, 45v128161 read to restore to read operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm read read pre row 0 col. 4 col. 0 banka l q1-4 q1-1 q1-0 0 2345678 1 t ras t rcd hi-z l restore termination ( read latency = 2, burst length = 4 ) segment channel 1 rst act (r) banka banka channel 1 channel 1 remark act(r) command is act command after rst command. without auto precharge t rad read to restore to write operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm read writ pre row 0 col. 5 col. 0 banka l q1-1 q1-0 d1-6 d1-5 0 2345678 1 t ras t rcd hi-z restore termination ( read latency = 2, burst length = 4 ) segment channel 1 rst act (r) banka banka channel 1 channel 1 d1-7 remark act(r) command is act command after rst command. without auto precharge t rad data sheet e0025n10 61 pd45v128421, 45v128821, 45v128161 write to restore to write operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm writ writ pre row 0 col. 1 col. 0 banka l d1-1 d1-2 d1-0 d1-2 d1-1 0 2345678 1 t ras t rcd hi-z restore termination mask ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 channel 1 d1-3 remark act(r) command is act command after rst command. without auto precharge write to restore to read operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm writ read pre row 0 col. 1 col. 0 banka l d1-1 d1-2 d1-0 q1-1 0 2345678 1 t ras t rcd hi-z restore termination mask ( read latency = 2, burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 channel 1 remark act(r) command is act command after rst command. without auto precharge data sheet e0025n10 62 pd45v128421, 45v128821, 45v128161 prefetch to prefetch operation without auto precharge clk command channel address a13 a10 dq dqm act act pfc row 0 row 1 banka bankb bankb 0 2345678 1 t rrd t apd t ppd hi-z l segment 1 channel 1 without auto precharge 910 pfc bankb segment 2 channel 8 without auto precharge pfc banka segment 3 channel 2 without auto precharge t ppd prefetch to restore operation without auto precharge (other bank restore) clk command channel address a13 a10 dq dqm act pfc row 0 banka row 0 banka 0 2345678 1 t apd t prd hi-z l segment 1 channel 1 t rad rst act (r) bankb bankb channel 2 segment 1 remark act(r) command is act command after rst command. without auto precharge without auto precharge data sheet e0025n10 63 pd45v128421, 45v128821, 45v128161 prefetch operation with auto precharge clk command channel address a13 a10 dq dqm act act pfc a row 0 banka row 0 banka banka 0 23456789 1 t apd t pal t rc hi-z l auto precharge segment 1 channel 1 data sheet e0025n10 64 pd45v128421, 45v128821, 45v128161 restore to prefetch operation without auto precharge clk command channel address a13 a10 dq dqm pfc pre row 0 bankb row 1 l banka 0 2345678 1 t ras t rrdr t rpd hi-z l segment 1 channel 2 t rad rst act (r) banka banka rst act (r) bankb bankb channel 1 channel 1 segment 3 segment 2 remark act(r) command is act command after rst command. t rad without auto precharge without auto precharge without auto precharge restore operation with auto precharge clk command channel address a13 a10 dq dqm row 0 banka 0 23456789 1 t rc hi-z l row 0 row 1 auto precharge segment 1 channel 2 t rad rsta act (r) banka banka t rad bankb bankb segment 3 channel 1 t rrdr act rst act (r) remark act(r) command is act command after rst command. without auto precharge data sheet e0025n10 65 pd45v128421, 45v128821, 45v128161 read to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 q1-8 q1-9 q1-10 q1-11 q1-0 q1-1 q1-2 q1-3 read col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. read will be interrupted by pfr. prl=4 (prefetch read latency) 13 t pal (read latency = 2, prefetch read latency = 4, burst length = 4) write to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 d1-8 d1-9 d1-10 q1-0 q1-1 q1-2 q1-3 writ col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. writ will be interrupted by pfr. prl=4 (prefetch read latency) l t pal (read latency = 2, prefetch read latency = 4, burst length = 4) data sheet e0025n10 66 pd45v128421, 45v128821, 45v128161 auto refresh operation clk command address a10 dq dqm h pall ref act 0 2349101112 1 t rp t rcf hi-z l self refresh operation (entry and exit) 109 clk command address a10 dq dqm 0 23456 1 t rp l pall h 96 98 99 100 101 108 97 ref t rcf act cke self refresh entry self refresh exit data sheet e0025n10 67 pd45v128421, 45v128821, 45v128161 10. package drawing notes 1. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2. dimension "a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. m p a g c n b m d l k j h i e f detail of lead end s 54 28 127 s item b c i l m n 54-pin plastic tsop ( ii ) (10.16 mm (400)) a d e f g h j p millimeters 0.80 (t.p.) 0.91 max. 0.13 0.50 0.10 10.16 0.10 0.10 22.22 0.05 0.10 0.05 0.32 1.1 0.1 11.76 0.20 1.00 + 0.08 ? 0.07 0.80 0.20 3 + 7 ? 3 k 0.145 + 0.025 ? 0.015 s54g5-80-9jf-2 data sheet e0025n10 68 pd45v128421, 45v128821, 45v128161 11. recommended soldering condition please consult with our sales offices for soldering conditions of the pd45v128 . type of surface mount device pd45v128421g5 : 54-pin plastic tsop (ii) (10.16mm (400)) pd45v128821g5 : 54-pin plastic tsop (ii) (10.16mm (400)) pd45v128161g5 : 54-pin plastic tsop (ii) (10.16mm (400)) data sheet e0025n10 69 pd45v128421, 45v128821, 45v128161 12. revision history edition / page description date this edition previous edition type of revision location nec corporation (m15076e) 1st edition / ? ? ? ? sep. 2000 2nd edition / p. 2 p. 2 deletion -a10 sep.2000 p. 9 p. 9 modification block diagram p. 35 p. 35 deletion 100 mhz p. 39, 40, p. 39, 40, deletion -a10 specs 42, 43, 44 42, 43, 44 elpida memory, inc. (e0025n) 1st edition / ? ? ? republished by elpida memory, inc. jan. 2001 data sheet e0025n10 70 pd45v128421, 45v128821, 45v128161 [memo] data sheet e0025n10 71 pd45v128421, 45v128821, 45v128161 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. pd45v128421, 45v128821, 45v128161 [memo] the names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company. m8e 00. 4 the information in this document is current as of november, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of elpida's data sheets or data books, etc., for the most up-to-date specifications of elpida semiconductor products. not all products and/or types are available in every country. please check with an elpida memory, inc. for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of elpida. elpida assumes no responsibility for any errors that may appear in this document. elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of elpida semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while elpida endeavours to enhance the quality, reliability and safety of elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. elpida semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of elpida semiconductor products is "standard" unless otherwise expressly specified in elpida's data sheets or data books, etc. if customers wish to use elpida semiconductor products in applications not intended by elpida, they must contact an elpida memory, inc. in advance to determine elpida's willingness to support a given application. (note) (1) "elpida" as used in this statement means elpida memory, inc. and also includes its majority-owned subsidiaries. (2) "elpida semiconductor products" means any semiconductor product developed or manufactured by or for elpida (as defined above). ? ? ? ? ? ? |
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